Process for fabricating films of uniform properties on semiconductor devices

ABSTRACT

A process for forming a thin layer exhibiting a substantially uniform property on an active surface of a semiconductor substrate. The process includes varying the temperature within a reaction chamber while a layer of a material is formed upon the semiconductor substrate. Varying the temperature within the reaction chamber facilitates temperature uniformity across the semiconductor wafer. As a result, a layer forming reaction occurs at a substantially consistent rate over the entire active surface of the semiconductor substrate. The process may also include oscillating the temperature within the reaction chamber while a layer of a material is being formed upon a semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 09/323,497, filed Jun. 1, 1999, now U.S. Pat. No. 6,537,677, issued Mar. 25, 2003, which is a divisional of application Ser. No. 09/041,913, filed Mar. 13, 1998, pending.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to processes to form a film of substantially uniform properties on the active surface of a semiconductor substrate, such as a semiconductor wafer or other structure, of silicon, polysilicon, gallium arsenide, silicon on insulator (SOI), silicon on sapphire (SOS), silicon on glass (SOG) or any other material which is useful as a semiconductor substrate in integrated circuit applications. Particularly, the process of the present invention includes forming films upon a semiconductor substrate at non-steady state temperatures in order to facilitate the substantially uniform properties of such films. The present invention also relates to processes for forming thin films having substantially uniform properties across the surface of a semiconductor wafer or other substrate during the formation of a layer of a material thereupon by creating temperature gradients between the center and edge of the semiconductor wafer.

2. Background of Related Art

As the integrated circuitry that is carried upon semiconductor substrates becomes ever-smaller and the surface area of such devices becomes ever-larger, the thermal output of such devices increases. Inconsistencies in the properties of the electrically conductive, semiconductive, and non-conductive layers of a semiconductor wafer including, without limitation, thickness, sheet resistance, reflectivity, transmissivity, absorptivity, dielectric constant, and various other characteristics of such layers, affect the electrical performance of semiconductor substrates, and therefore contribute, in part, to increased heat output, consequently higher operating temperatures, and other inefficiencies of many state-of-the-art semiconductor substrates.

The formation of films of substantially uniform properties on semiconductor wafer or other substrate active surfaces requires control over the rate at which chemical reactions occur over the active surface. Since elevated temperatures drive these layer-forming reactions, the ability to control the uniform distribution of reactants over a semiconductor wafer's active surface is affected by the temperature of the region of the semiconductor wafer that lies therebeneath and the concentration of the reactants thereabove. If the temperature is uniform (i.e., a temperature gradient does not exist) across the active surface of a semiconductor wafer, reaction rate gradients may develop thereover, which phenomenon leads to variations in the properties of the layers formed on the active surface. Thus, during the fabrication or formation of layers on semiconductor wafers, a lack of temperature gradients thereacross is undesirable.

Various techniques are known in the art for forming layers on the active surface of semiconductor wafers or other substrates. One such technique, known as single wafer optical processing, combines low thermal mass photon-assisted rapid wafer heating with reactive ambient semiconductor processing. Optical processing permits the rapid alteration of both the temperature of the semiconductor substrate and the process environment. Consequently, each of the fabrication steps and their sub-processes may be independently optimized in order to improve the overall electrical performance of the resulting semiconductor substrates.

Another technique that is conventionally employed to form layers on the active surface of semiconductor substrates is known as rapid thermal processing (RTP). Rapid thermal processing techniques typically employ radiant energy to heat the semiconductor substrate to very high temperatures (e.g., 420° C. to 1150° C.) for short time periods. The widespread use of rapid thermal processing may, in part, be due to the repeatable quality of the films formed thereby. Rapid thermal processing may be employed to form oxide layers, nitride layers, doped layers, and to perform different types of thermal anneals of layers on semiconductor substrates.

Similarly, several types of chemical vapor deposition chambers and techniques are conventionally employed to form dielectric layers (e.g., oxides, nitrides, and advanced dielectrics), semiconductor layers (e.g., amorphous silicon and polysilicon), and electrically conductive layers (e.g., aluminum, copper, tungsten, and titanium nitride), on semiconductor substrate active surfaces.

Many such techniques, however, are unable to generate or maintain substantially uniform amounts of layer-forming reactions across the surface of semiconductor wafers and, therefore, do not form thin films of uniform properties upon the active surface of semiconductor wafers. Such conventional layer formation techniques typically utilize steady-state conditions (i.e., the reaction temperature is maintained within a typically small predetermined range), which often permit the formation of significant reaction rate gradients across the active surface of the semiconductor wafer, thereby limiting the uniformity of films formed thereon. Thus, by maintaining a stable temperature during layer formation, many of these conventional systems actually impede a uniform reaction across the surface of the semiconductor wafers. Consequently, layers of non-uniform properties form on the semiconductor wafers. Further, with many of the current layer formation techniques, as the size of semiconductor wafers increases, and larger non-wafer semiconductor substrates become more commonly used, variations in layer properties become more pronounced due to the greater depletion of reactants over some regions thereof than other regions thereof.

U.S. Pat. No. 5,635,409 (“the '409 patent”), issued to Mehrdad M. Moslehi on Jun. 3, 1997, discloses a control system and process which attempt to reduce or eliminate the development of temperature gradients (i.e., optimize process uniformity) over semiconductor wafer active surfaces during each of the heat-up, steady-state heating and cool-down phases by monitoring and adjusting the reaction chamber temperature at various locations. According to the process of the '409 patent, the semiconductor substrate and reaction chamber temperatures are adjusted in a linear fashion during the heat-up and cool-down phases.

However, use of the control system of the '409 patent is somewhat undesirable since it creates and maintains a substantially uniform or “steady state” temperature over the semiconductor wafer which, as explained above, does not facilitate, and actually impedes, reaction rate uniformity. Moreover, due to the ever-increasing size of semiconductor wafers and other substrates, the maintenance of a constant temperature over the surface of such semiconductor wafers may further decrease the uniformity of properties of thin films formed thereon.

The generation and maintenance of a uniform temperature across a semiconductor wafer may, however, be desirable while forming layers of some materials on the semiconductor wafer. For example, uniform semiconductor wafer temperatures are desirable during dopant diffusion processes, metal salicidation processes, and where multiple layers having different coefficients of expansion are being formed upon the semiconductor wafer and annealed to one another. Conventional layer formation processes which generate and maintain uniform semiconductor wafer temperatures, however, may also induce stress on the semiconductor wafer, which may in turn cause lattice defects in the semiconductor wafer, such as point, line, or area slip defects.

Thus, a need exists for a process for forming films of substantially uniform properties on the active surface of semiconductor substrates, while reducing stress on the semiconductor substrates.

SUMMARY OF THE INVENTION

The present invention addresses each of the foregoing needs by forming material layers upon a semiconductor substrate under non-steady state temperature conditions. Stated another way, the inventive process forms layers during non-steady state phases, such as ramp-up and ramp-down of the reaction chamber temperature, rather than during a phase where the temperature of a reaction chamber or furnace is held steady.

In a first embodiment of the process of the present invention, a layer is formed upon a semiconductor substrate during a ramp-up of the reactor temperature. Deposition under such conditions of increasing temperature facilitates the formation of a layer of substantially uniform properties over the semiconductor substrate. The first embodiment of the process of the present invention is particularly useful for forming layers of materials upon semiconductor substrates, which materials, where used to form layers by conventional steady-state techniques, typically result in a material layer thinner at the edge region of a semiconductor substrate than at the center region thereof.

A second embodiment of the process of the present invention includes the formation of a material layer during a controlled ramp-down of the reactor temperature, during which the temperature at the edge region of the semiconductor substrate is cooler than that at the center region thereof. The second embodiment facilitates the formation of uniform property layers of materials which, where employed with conventional steady-state layer forming techniques, typically result in layers thicker at the edge regions of a semiconductor substrate than at the center region thereof.

In both the first and second embodiments of the inventive process, a layer may be formed in multiple steps, where more than one ramp-up or ramp-down is employed in order to form the layer.

In another embodiment of the inventive process, the reaction chamber temperature is intermittently varied, continually fluctuated or oscillated in order to provide a substantially uniform reaction over the semiconductor substrate while forming a layer thereon. Such fluctuation in the temperature of the reaction chamber may be effected during the ramp-up, the ramp-down, and/or the so-called “steady state” temperature trends. During such fluctuation of the temperature of the reaction chamber, the temperature profile, plotted temperature (y-axis coordinate) over time (x-axis coordinate), may have a saw-tooth (i.e., linear, with small variations) or a humped configuration. Such variation of the reaction temperature equalizes the reaction rate across the surface of the semiconductor substrate and may be effected by existing fabrication equipment.

Semiconductor substrates which include material layers formed in accordance with the processes of the present invention are also within the scope of the present invention.

Other advantages of the present invention will become apparent to those of ordinary skill in the relevant art through a consideration of the appended drawings and the ensuing description.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a line graph illustrating the heat-up phase temperatures, plotted over time, at which a layer of a material may be formed upon a semiconductor wafer in accordance with a first embodiment of the process of the present invention;

FIG. 2 is a line graph which depicts a variation of the process of FIG. 1, wherein the heat-up phase and deposition during the same are repeated;

FIG. 3 is a line graph illustrating the cool-down phase temperatures, plotted over time, at which a layer of a material may be formed upon a semiconductor wafer in accordance with a second embodiment of the process of the present invention;

FIG. 4 is a 49 point contour map which depicts a silicon nitride layer that was formed by prior art techniques;

FIG. 5 is a 49 point contour map which depicts a layer that was formed in accordance with a second embodiment of the process of the present invention;

FIG. 6 is a line graph which depicts a variation of the process of FIG. 3, wherein the cool-down phase and deposition during the same are repeated;

FIG. 7 is a line graph which illustrates the heat-up phase temperatures over time as another embodiment of the process of the present invention is employed to form a layer upon a semiconductor wafer;

FIG. 7a is a line graph which illustrates the heat-up phase temperatures over time as a variation of the process of FIG. 7 is employed to form a layer upon a semiconductor wafer;

FIG. 8 is a line graph which illustrates the deposition phase temperatures over time as the process of FIG. 7 is employed to form a layer upon a semiconductor wafer;

FIG. 9 is a line graph which illustrates the cool-down phase temperatures over time as the process of FIG. 7 is employed to form a layer upon a semiconductor wafer;

FIGS. 10a through 10 e are line graphs which illustrate use of the process of FIG. 7 during different deposition phases;

FIG. 11 is a schematic cross-sectional view of a semiconductor substrate which includes a layer of substantially uniform properties which has been formed in accordance with the process of the present invention; and

FIG. 12 is a schematic cross-sectional representation of a reaction chamber with semiconductor wafers positioned therein.

DETAILED DESCRIPTION OF THE INVENTION

The process of the present invention includes the formation of a material layer, or film, upon an active surface of a semiconductor wafer or other substrate under non-steady state temperature conditions. “Non-steady state,” as used herein, refers to varying, oscillating, continually fluctuating, or summing reaction chamber temperatures with one or more signals of varying frequency, amplitude or phase. Such layers or films may be formed by known deposition or growth techniques or reactions that are modified by employing temperature variation according to the process of the present invention, and using known equipment programmed to effect such temperature variation during the formation of the layer or film. Such deposition and growth techniques include introducing into the reaction chamber matter of a type that promotes the formation of a material layer upon the substrate in proximity to an exposed surface of the substrate.

Temperature variation according to the process of the present invention may be effected by altering one or more characteristics of the power that is required by a heat generating source, such as a conventional furnace or a rapid thermal processing system. Various characteristics of the power that may be altered in order to effect temperature variation include frequency, amplitude and phase. Similarly, multiple power frequencies may be summed. Altering such characteristics of the heat-generating power facilitates creation of temperature variations of virtually any profile, as may be illustrated by a line graph wherein temperature is plotted over time. Alternatively, the temperature variation of the process of the present invention may be effected by setting the process chamber to a predetermined, fixed temperature profile, which is also referred to as a temperature set point profile. A feedback control system of the type known in the art may be employed to alter the amount of power that is input into the process chamber in order to increase, maintain, or reduce the amount of heat that is generated in the process chamber and thereby substantially emulate the temperature set point profile.

The use of non-steady state temperature conditions facilitates the formation of a layer of a material that includes substantially uniform properties. The term “properties” is used herein as comprising one or more of the thickness, sheet resistance, reflectivity, transmissivity, absorptivity, dielectric constant, and various other characteristics of the layer.

With reference to FIG. 1, which is a line graph that depicts the temperature of a reaction chamber (y-axis) plotted against time (x-axis), a first embodiment of the process of the present invention includes forming a material layer upon a semiconductor wafer during a heat-up phase, which is typically referred to as a ramp-up of the temperature of the environment that surrounds the semiconductor wafer, which is also referred to for simplicity as the reaction chamber temperature. Thus, the layer is formed while the temperature of the semiconductor wafer increases from a first temperature, represented as , to a second temperature, represented as X. As those of skill in the art are aware, as the reaction chamber temperature is increased, a semiconductor wafer's edge region heats up more quickly than its center region. Thus, during the heat-up phase, the edge region of the semiconductor wafer is typically a higher temperature at a given point in time than the center region of the same.

The first embodiment of the process is particularly useful for enhancing the uniformity of materials that, under steady state reaction chamber temperature conditions, form thicker layers at the center region of a semiconductor wafer than at the edge region of the same due to a higher reaction rate at the center region than at the edge region since, in some layer formation processes, fewer reactants are available at the edge region than at the center region of a semiconductor wafer, which may result in the formation of a layer with a “convex” or “dome” (i.e., inverted “bowl” or “dish”) shaped contour. Thus, the process of the present invention is useful for preventing the “convex” or “dome” (i.e., inverted “bowl” or “dish”) shaped contours of layers that are typically formed by many conventionally employed processes which deposit or grow layers on semiconductor wafers under steady state temperature conditions. As explained previously, such non-uniformities are typically caused by the differential depletion of reactants, or the creation of reactant gradients, over the surface of the semiconductor wafer.

The formation of a doped amorphous silicon layer of substantially uniform properties is exemplary of the first embodiment of the process of the present invention. Typical conventional doped amorphous silicon deposition techniques, such as the exemplary process that is disclosed in U.S. Pat. No. 4,963,506 (“the '506 patent”), which issued to Hang M. Liaw, et al. on Oct. 16, 1990, the disclosure of which is hereby incorporated by reference in its entirety, occur under steady state conditions within a reaction chamber that has been heated to between about 500° C. and 600° C. In contrast, the deposition of doped amorphous silicon in accordance with the first embodiment of the present invention occurs while the reaction chamber temperature is being increased to about 600° C. First, a semiconductor wafer upon which the doped amorphous silicon layer is to be formed is placed into a reaction chamber while the temperature within the chamber is held at “idle” (e.g., a temperature of about 500° C.). The temperature within the reaction chamber is then increased. As the reaction chamber reaches a desirable initial deposition temperature (e.g., about 525° C. for doped amorphous silicon), the appropriate, conventionally employed reactants are introduced therein. The rate at which the reaction chamber temperature is subsequently increased and the amount of the temperature increase is dependent upon several factors, including without limitation the specific type of material that is being deposited, the desired layer properties and the desired level of layer uniformity. The introduction of reactants into the reaction chamber continues until the temperature within the reaction chamber reaches a desired terminal deposition temperature (e.g., about 500° C. to 550° C. for doped amorphous silicon), at which temperature the introduction of reactants is stopped. Subsequently, the temperature within the reaction chamber is decreased to the “idle” temperature and the semiconductor wafer may be removed therefrom.

For the purpose of comparison, a layer of doped amorphous silicon was formed upon a semiconductor wafer in accordance with a conventional steady state deposition technique while the semiconductor wafer was being rotated. The doped amorphous silicon layer had a “convex” or “dome” shaped contour, indicating that the doped amorphous silicon layer is thicker at the center region of the semiconductor wafer than at the edge region of the same. The doped amorphous silicon layer that was deposited by a prior art technique varied about 35 Å from its thickest measured point (1015.81 Å), near the center region of the semiconductor wafer, to its thinnest measured point (979.33 Å), near the wafer's edge region, which is a variation of about 3.5% from the median thickness (about 1002 Å) of the layer; thus, the standard deviation of the variation in thickness was about 1.2%.

In contrast, a doped amorphous silicon layer that was formed on a semiconductor wafer in accordance with the first embodiment of the inventive process, as explained above, exhibited a more uniform thickness than that of the conventional technique described in the preceding paragraph, as evidenced by the lack of an inverted “bowl” or “dish” shaped contour. Stated in relative terms, the doped amorphous silicon layer varied only about 8 Å from its thickest measured point (1003.72 Å) to its thinnest measured point (995.65 Å), which is a variation of only about 0.8% from the median thickness (1001.20 Å) of the layer; thus, the standard deviation of the variation in thickness was only about 0.25%. The doped amorphous silicon layer that was formed in accordance with the first embodiment of the inventive process had about one-fifth to about one-sixth the variation in thickness of the doped amorphous silicon layer as a doped amorphous silicon layer of similar overall thickness that was deposited under prior art steady state temperature conditions.

Similarly, a layer of doped polysilicon may be formed in accordance with the first embodiment of the inventive process. Typical conventional doped polysilicon deposition techniques, such as the exemplary process that is disclosed in the '506 patent, occur under steady state conditions within a reaction chamber that has been heated to between about 600° C. and 700° C. In contrast, the deposition of doped polysilicon in accordance with the first embodiment of the present invention occurs while the reaction chamber temperature is being increased from an initial temperature to about 580° C. to about 680° C., or as high as about 800° C. First, a semiconductor wafer upon which the doped amorphous silicon layer is to be formed is placed into a reaction chamber while the temperature within the chamber is held at “idle” (e.g., a temperature of about 500° C.). The temperature within the reaction chamber is then increased. As the reaction chamber reaches a desirable initial deposition temperature (e.g., about 575° C. to about 585° C. for doped polysilicon), the appropriate, conventionally employed reactants are introduced therein. The introduction of reactants into the reaction chamber continues until the temperature within the reaction chamber reaches a desired terminal deposition temperature (e.g., about 675° C. for doped polysilicon). Subsequently, the temperature within the reaction chamber is decreased to the “idle” temperature and the semiconductor wafer may be removed therefrom.

The line graph of FIG. 2 depicts a variation of the first embodiment wherein, following the formation of a portion of a layer while the temperature of the reaction temperature is between first temperature  and second temperature X and reduction of the temperature within the reaction chamber, the heat-up phase may be repeated at least once to form another portion of the layer. Such repetitious heating-up is particularly useful for forming layers of materials which require a large increase in temperature over a relatively short period of time. Preferably, when such repetitious heating is employed in accordance with the first embodiment of the process, layer formation is effected only during the heat-up phases of the cycle (i.e., during temperature increases).

FIG. 3 illustrates a second embodiment of the process of the present invention, wherein a layer is formed upon a semiconductor wafer during a cool-down phase, which is typically referred to as a ramp-down in the reaction chamber temperature. Formation of the layer begins after the temperature within the reaction chamber reaches a first temperature , and continues until the temperature within the reaction chamber drops to a second temperature X. Thus, deposition occurs in accordance with the second embodiment of the process as the semiconductor wafer is cooled down. Preferably, the temperature within the reaction chamber is decreased at a controlled rate. The amount of temperature decrease and the rate at which the temperature is decreased are dependent upon the material from which a layer is formed. As those of skill in the art are aware, a semiconductor wafer's edge region cools at a faster rate than the center region of the same. Thus, during the cool-down phase, the temperature of the edge region of the semiconductor wafer is typically lower at a given point in time than that of its center region.

The second embodiment of the inventive process is particularly useful for facilitating the formation of layers of substantially uniform properties from materials that, under steady state temperature conditions, form thinner layers at the center region of a semiconductor wafer than at its edge region. Thus, the second embodiment of the process is useful for preventing the formation of layers having concave “bowl” or “dish” shaped contours, which may occur when conventional techniques are employed.

For example, when conventional low pressure chemical vapor deposition (LPCVD) techniques, such as the exemplary process that is disclosed in U.S. Pat. No. 4,395,438 (“the 438 patent”), which issued to Ping-Wang Chiang on Jul. 26, 1983, the disclosure of which is hereby incorporated by reference in its entirety, are employed to form silicon nitride (Si₃N₄) layers on semiconductor wafers, the steady state temperatures within the reaction chamber are typically in the 700° C. to 800° C. range. Silicon nitride deposition in accordance with the process of the present invention includes a controlled ramp-down of the temperature within the reaction chamber from about 780° C. to about 645° C., during which the appropriate, conventionally employed chemical reactants are introduced into the reaction chamber.

FIGS. 4 and 5 are 49 point contour maps of semiconductor wafers bearing thick (i.e., 1,800 Å to 2,000 Å) silicon nitride layers. The contour map of FIG. 4 illustrates the thickness of a silicon nitride layer that has been formed upon a semiconductor wafer in a hot wall furnace by conventional steady state temperature deposition techniques. The silicon nitride layer shown in FIG. 4 has a “bowl” or “dish” shaped contour, which is typically caused by reactant gradients over the surface of a semiconductor wafer. As noted previously, when conventional techniques are employed which utilize steady state temperatures throughout the reaction chamber, the reaction rate of the edge region of a semiconductor wafer is higher than the temperature of the center region of the same. Additionally, it is known in the art that thicker layers of some materials form upon the higher temperature regions of a semiconductor wafer than upon the lower temperature regions thereof. Consequently, the use of steady state reaction temperatures throughout a deposition process may result in the formation of a silicon nitride layer having non-uniform properties due to the generation of reactant gradients thereabove. As illustrated by FIG. 4, the layer is thicker at the edge region of the semiconductor wafer than at its center region. The thickness of the silicon nitride layer varied, from its thinnest measured point (1,808.59 Å) to its thickest measured point (1,874.90 Å), by about 66 Å, which is about 3.6% of the total average layer thickness (1,833.47 Å); thus, the standard deviation in layer thickness was about 1.1%.

In contrast, FIG. 5 is a contour map which depicts the thickness of a silicon nitride layer that has been formed upon a semiconductor wafer in accordance with the second embodiment of the process of the present invention (i.e., during a cool-down phase). The silicon nitride layer of FIG. 5 has a more uniform thickness than that of FIG. 4. The silicon nitride layer varied about 48 Å from its thickest measured point (1,859.97 Å) to its thinnest measured point (1,811.57 Å), which is a variation of about 2.6% from the median thickness (1,836.30 Å) of the layer; thus, the standard deviation of the variation in thickness was only about 0.75%. Moreover, the thickness of the silicon nitride layer depicted in FIG. 5 does not create the bowl-shaped contour of FIG. 4, indicating that when the process of the present invention is employed in order to form a silicon nitride layer upon a semiconductor wafer, the rate at which such a layer is formed on the edge region of the semiconductor wafer is not significantly higher than the rate at which a layer is formed on the center region of the same.

Similarly, an oxide layer may be formed upon a semiconductor wafer in accordance with the second embodiment of the present invention by techniques that employ tetraethyl-ortho-silicate (TEOS), such as the exemplary process that is disclosed in U.S. Pat. No. 4,872,947 (“the 947 patent”), which issued to David N. Wang et al. on Oct. 18, 1989, the disclosure of which is hereby incorporated by reference in its entirety. A semiconductor wafer upon which a layer of TEOS is to be formed is positioned within a reaction chamber while the temperature within the chamber is at an “idle” temperature for conventional TEOS layer formation, about 500° C. The temperature within the reaction chamber is then increased to at least about the temperature at which TEOS layer formation by conventional processes occurs, about 600° C. to about 625° C., which is referred to as a first temperature. A controlled ramp-down of the temperature within the reaction chamber to a second, or termination, temperature is then effected. During the controlled ramp-down, the appropriate, conventionally employed chemical reactants are introduced into the reaction chamber, wherein a TEOS layer forms on a surface of the semiconductor wafer. After a TEOS layer of the desired thickness has been formed, the temperature within the reaction chamber may be reduced to “idle” and the semiconductor wafer removed therefrom.

A TEOS layer that has been formed in accordance with the second embodiment of the process of the present invention has substantially uniform properties. Such an exemplary TEOS layer, which was formed upon a semiconductor wafer that was positioned centrally in a reaction chamber, varied only about 38 Å from its thickest measured point (1511 Å) to its thinnest measured point (1474 Å), which is a variation of only about 2.5% from the median thickness (1484 Å) of the TEOS layer. In contrast, a TEOS layer that was formed under steady state conditions by conventional processes varied about 104 Å from its thickest measured point (1557 Å) to its thinnest measured point (1453 Å), which is a variation of about 7.0% from the median thickness (1496 Å) of the conventionally-formed TEOS layer.

Similarly, in comparison to conventional layer forming techniques, the second embodiment of the process of the present invention was useful for forming TEOS layers of substantially uniform properties upon semiconductor wafers that were positioned near the top and near the bottom of the reaction chamber. A TEOS layer that was formed upon a semiconductor wafer that was positioned near the top of the reaction chamber, and in accordance with the second embodiment, varied about 70.4 Å from its thickest measured point to its thinnest measured point, with a mean thickness of 1465.4 Å. Thus, the TEOS layer had a thickness variation of 4.8% of the mean layer thickness. In contrast, the variation in thickness (114.9 Å) of a conventionally formed TEOS layer that was formed upon a similarly positioned semiconductor wafer varied 7.8% from the mean thickness (1471.7 Å) thereof.

Similar results occurred when TEOS layers were formed on semiconductor wafers that were positioned near the bottom of the reaction chamber. When the second embodiment of the inventive process was employed, the variation in thickness of the TEOS layer was 4.5% (a range of 64.6 Å) of the mean thickness (1433.3 Å) of the same. A conventionally formed TEOS layer, however, varied 9.6% (a range of 147.0 Å) from the mean thickness (1527.8 Å) thereof. Thus, the TEOS layer that was formed in accordance with the second embodiment of the process of the present invention had about one-half to about one-third of the thickness variation of the conventionally formed TEOS layer.

FIG. 6 is a line graph which illustrates the temperature of a reaction chamber plotted over time during repetitious cool-down phases. Similar to the repetitious heating-up that was explained above in reference to the first embodiment of the inventive process, a variation of the second embodiment of the inventive process includes the repetitious cooling-down of the temperature within the reaction chamber from first temperature  to second temperature X in order to facilitate the formation of a substantially uniform layer upon a surface of a semiconductor wafer. Such repetitious cooling-down is particularly useful for forming layers of materials that require a small temperature change and for forming layers which require a large decrease in temperature over a relatively short period of time. Preferably, when such repetitious cooling-down is employed, layer formation is effected only during the cool-down portions of the cycle.

In another embodiment of the layer formation process of the present invention, the temperature within the reaction chamber may be oscillated, fluctuated, or intermittently varied during at least a portion of any of the heat-up, substantially steady state, or cool-down phases, or any combination thereof. Such intermittent variation of the temperature generates and maintains a substantially uniform temperature over the surface of a semiconductor wafer. Temperature uniformity over the surface of a semiconductor wafer is desirable for layer forming processes including, without limitation, dopant diffusion, alloying or any other diffusion-limited process, and the formation of multiple layers having different coefficients of expansion. Additionally, the generation of substantially uniform temperature over a semiconductor wafer may reduce or eliminate stresses that may result in the formation of lattice defects, such as point, line (e.g., slip, straight dislocations, dislocation loops, etc.), area, volume, or other thin film defects.

During the heat-up phase, the process of the present invention may include an oscillating increase in the temperature within the reaction chamber. As the temperature within the reaction chamber is ramped up during the heat-up phase, each increase in reactor temperature is followed by a temperature decrease. As illustrated by FIG. 7, a linear graph of such a heat-up phase, wherein temperature is plotted over time, includes fluctuations in temperature which impart the graph with a saw tooth, or a zig-zag, configuration. Other oscillating heat-up patterns are also within the scope of the present invention, as are less predictable variations in the reactor temperature during the heat-up or anneal phases. The amount of temperature variation between the high and low points of each zig-zag and the durations of each temperature increase and subsequent temperature decrease are optimized in order to provide uniform temperatures across the semiconductor wafer at all times during the formation of a layer or film thereon. This embodiment of the present invention facilitates a uniform cross-wafer temperature during either of the heat up or cool down phases. Although the graph of FIG. 7 represents each fluctuation as an increase in temperature followed by a smaller decrease in temperature, temperature increases that are followed by no change (as illustrated by FIG. 7a) in temperature for a period of time or by lower rate temperature increases are also within the scope of the present invention.

The oscillating increase in the reaction chamber temperature during the heat-up phase facilitates a uniform increase in the temperature across the various regions of a semiconductor wafer, including its edge region and center region. As those of skill in the art are aware, as the temperature within many conventional reaction chambers is increased, a semiconductor wafer's edge region heats up more quickly than its center region. Thus, during the heat-up phase, the rate at which the temperature of the center region of a semiconductor wafer increases typically lags behind the rate at which the temperature of its edge region increases. Similarly, the rate at which the temperature of the center region decreases lags behind the rate at which the temperature of the wafer's edge region decreases. By intermittently decreasing the temperature within the reaction chamber for short periods of time, the temperature of the edge region of a semiconductor wafer decreases, while the temperature of the center region remains substantially the same, permitting the temperature of the center region of a semiconductor wafer to “catch up” to the temperature at the edge region of the wafer, thereby equalizing the temperature across the semiconductor wafer's active surface during the heat-up phase, and reducing or eliminating the generation of any temperature gradients thereon in order to facilitate the formation of a layer of substantially uniform properties thereupon and reducing the amount of stress that is induced on a semiconductor wafer, thereby potentially decreasing the occurrence of semiconductor wafer lattice defects, such as point, line, and area slip defects.

Oscillation of the temperature within the reaction chamber may also be effected during a so-called “steady state,” or “conventional” anneal phase, which is also referred to as a substantially steady state temperature trend. As in the heat-up phase, oscillation, fluctuation, or intermittent variation of the temperature within the reaction chamber maintains a substantially uniform temperature over the surface of a semiconductor wafer during the “conventional” anneal phase. FIG. 8 is a line graph which illustrates the temperature within the reaction chamber plotted over time during a “conventional” anneal phase. Although the graph line is saw tooth configured, as explained previously, each temperature increase is not necessarily followed by a decrease in temperature. Similarly, other oscillating heat-up patterns and less predictable variations in the temperature of the surrounding environment during the “conventional” anneal phase are also within the scope of the present invention. During the “conventional” anneal phase, the temperature may remain within a predetermined range.

Varying the reactor temperature to which a semiconductor wafer is subjected during a “conventional” anneal phase has essentially the same effect as described above in reference to the heat-up phase. Under steady state temperature conditions, the edge region of a semiconductor wafer absorbs thermal energy more quickly than the wafer's center region, which may create a temperature gradient over the active surface of the wafer. The edge region of a semiconductor wafer also, however, dissipates thermal energy at a higher rate than the center region. Thus, by constantly varying the reactor temperature during the “conventional” anneal phase, the semiconductor wafer's temperature substantially equalizes, facilitating the maintenance of a substantially uniform temperature over all regions of the semiconductor wafer.

Temperature oscillation during the cool-down phase, similar to that described above in reference to the heat-up and “conventional” anneal phases, may also be employed in accordance with the process of the present invention. The edge region of a semiconductor wafer dissipates thermal energy (i.e., cools down) more quickly than the wafer's center region. Stated another way, the rate at which the center region of a semiconductor wafer cools is less than the rate at which its edge region cools. Since the layer formation may continue into the cool-down phase, it is necessary to control the temperature so as to maintain a uniform temperature across the semiconductor wafer's active surface during that phase. By intermittently increasing or maintaining the temperature within the reaction chamber during the cool-down phase, thermal energy is added to the cooler edge region of a semiconductor wafer. Thus, the wafer's edge region is heated up to equalize temperatures across the wafer during the cool-down phase.

Referring now to FIG. 9, which is a line graph which illustrates the temperatures of the cool-down phase over time as the temperature oscillation process of the present invention is employed to form a layer upon a semiconductor wafer, the temperature is intermittently varied, as described above in reference to the heat-up and “conventional” anneal phases.

Maintaining a uniform temperature across a semiconductor wafer during the cool-down phase may also prevent the formation of any discontinuities or other flaws that may be induced by non-uniform cooling of the newly formed layer and/or the semiconductor wafer.

FIGS. 10a through 10 e are line graphs which illustrate some of the different temperature trends during which temperature oscillation within the reaction chamber according to the present invention may be utilized. In FIG. 10a, the temperature within the reaction chamber is continually fluctuated during each of the heat-up, anneal, and cool-down phases. FIG. 10b illustrates fluctuation of the temperature within the reaction chamber in the heat-up phase only. FIG. 10c illustrates temperature fluctuation of the reaction chamber temperature only during the “conventional” anneal phase. FIG. 10d shows fluctuation of the temperature within the reaction chamber during the “conventional” anneal phase and the beginning of the cool-down phase. FIG. 10e depicts fluctuation of the temperature within the reaction chamber during the heat-up phase, the “conventional” anneal phase, and at the beginning of the cool-down phase. Similarly, the temperature within the reaction chamber may be fluctuated during any temperature trend during which a layer is formed upon a semiconductor wafer and during the subsequent cooling of the layer and the wafer, including during brief segments of a larger temperature trend.

The process of the present invention may also be employed to form other types of layers upon semiconductor wafers, including, without limitation, oxide, oxynitride, gate hardening, Si₃N₄ reoxidation, metal alloying, and other layers.

An exemplary material layer formation system, which is depicted in FIG. 12, includes a reaction chamber 20 with a heating element 22 therein. Semiconductor wafers 24 a, 24 b and 24 c upon which a material layer is to be formed are positioned in reaction chamber 20. Reaction chamber 20 is heated to a desired temperature by inputting power into heating element 22. As the temperature within reaction chamber 20 increases, the temperature of each of semiconductor wafers 24 a, 24 b and 24 c increases. When the temperature of reaction chamber 20 reaches a first, or initial anneal, temperature, matter 26 of a type that will promote the formation of a material layer upon each of semiconductor wafers 24 a, 24 b and 24 c is introduced into reaction chamber 20 through an inlet 28. Preferably, the introduction of matter 26 into reaction chamber 20 is continued until the reaction chamber reaches a second, or terminal anneal, temperature.

Preferably, in order to form uniform layers upon semiconductor wafers, the frequency and amount of temperature variation of the process of the present invention are optimized for the type of layer formed, the desired layer properties, and the equipment with which the layer is formed. Similarly, depending upon the initial growth pattern of a formed layer, the amount and rate of temperature variation may be altered or optimized in order to enhance uniformity in the properties of the layer. Moreover, repetition of the process, as well as oscillating the temperature within the reaction chamber, may be employed to form substantially uniform layers upon the surface of a semiconductor wafer.

Similarly, when the temperature within the reaction chamber is oscillated while a layer of a material is being deposited upon a semiconductor wafer, the amount or magnitude of oscillation, as well as the frequency of oscillation, may be altered and optimized in order to enhance uniformity in the layer's properties. Such alteration or oscillation may be responsive to the temperature at various regions of the semiconductor wafer, the initial growth pattern of the layer or a combination thereof.

The overall temperature trend (e.g., increasing, decreasing, steady state) may also be altered from a first trend, or first phase, to a second trend, or second phase, in order to enhance the uniformity in layer properties.

The process of the present invention may be employed by various types of existing systems including, without limitation, hot and cold wall, single wafer and multiple wafer, vertical and horizontal, plasma-enhanced systems with or without wafer rotation, atmospheric pressure, high pressure and low pressure reactors. The inventive process may also be used with systems which are typically incapable of maintaining uniform temperatures throughout their reaction chambers, and were, therefore, previously considered undesirable for forming certain types of layers. Advantageously, substantially uniform layers may be formed in existing semiconductor substrate fabrication equipment without requiring expensive modifications thereto or the replacement thereof.

Systems which monitor the temperatures of various regions of a semiconductor wafer, and which adjust the temperature within the reaction chamber so as to effect the formation of a layer of substantially uniform properties upon the wafer, including equalizing the temperature or the reaction rate across the wafer, may also be employed in combination with a process of the present invention in order to automate the process and enhance the uniformity of layers formed in accordance therewith. Systems which monitor the properties of a layer of a material during its formation upon a semiconductor wafer, as well as systems which monitor the overall growth pattern of a layer during its formation upon a semiconductor wafer, may also be employed in combination with a process of the present invention.

Referring now to FIG. 11, a semiconductor substrate 10 is depicted which includes a material layer 12 of substantially uniform properties that has been formed upon a substrate 14 in accordance with the process of the present invention. Preferably, material layer 12 has a variation in thickness, relative to the mean thickness of the material layer, of less than about 3.5%. Such semiconductor substrates are also within the scope of the present invention.

Although the foregoing description contains many specifics, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some of the presently preferred embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. Features from different embodiments may be employed in combination. The scope of this invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions and modifications to the invention as disclosed herein which fall within the meaning and scope of the claims are to be embraced thereby. 

What is claimed is:
 1. A semiconductor device structure comprising a substrate having a silicon layer formed thereover, said silicon layer having a total thickness variation of about 3.5% or less.
 2. The semiconductor device structure of claim 1, wherein said silicon layer comprises amorphous silicon.
 3. The semiconductor device structure of claim 2, wherein said amorphous silicon comprises doped amorphous silicon.
 4. The semiconductor device structure of claim 1, wherein said silicon layer comprises polysilicon.
 5. The semiconductor device structure of claim 4, wherein said polysilicon comprises doped polysilicon.
 6. A semiconductor device structure, comprising a silicon oxide layer formed thereover, said silicon oxide layer having a total thickness variation of less than about 4.8%.
 7. The semiconductor device structure of claim 6, wherein said silicon oxide layer comprises tetraethylorthosilicate (TEOS).
 8. The semiconductor device structure of claim 1, wherein said silicon layer has at least one substantially uniform property.
 9. The semiconductor device structure of claim 8, wherein said at least one substantially uniform property comprises at least one of sheet resistance, reflectivity, transmissivity, absorptivity, etch characteristics, dopant diffusion, and dielectric constant.
 10. A material layer formed over a semiconductor substrate, the material layer having a total thickness variation of about 2.6% or less.
 11. The material layer of claim 10, comprising silicon.
 12. The material layer of claim 11, wherein said silicon comprises amorphous silicon.
 13. The material layer of claim 12, wherein said amorphous silicon comprises doped amorphous silicon.
 14. The material layer of claim 10, comprising polysilicon.
 15. The material layer of claim 14, wherein said polysilicon comprises doped polysilicon.
 16. The material layer of claim 10, comprising a deposited dielectric material.
 17. The material layer of claim 16, wherein said deposited dielectric material comprises a silicon oxide.
 18. The material layer of claim 17, wherein said silicon oxide comprises tetraethylorthosilicate (TEOS).
 19. The material layer of claim 16, wherein said deposited dielectric material comprises a silicon nitride.
 20. The material layer of claim 10, having at least one substantially uniform property.
 21. The material layer of claim 20, wherein said at least one substantially uniform property comprises at least one of sheet resistance, reflectivity, transmissivity, absorptivity, etch characteristics, dopant diffusion, and dielectric constant.
 22. The semiconductor device structure of claim 1, wherein said total thickness variation is about 0.8% or less.
 23. The semiconductor device structure of claim 7, wherein said total thickness variation is about 4.5% or less.
 24. The semiconductor device structure of claim 7, wherein said total thickness variation is about 2.5% or less.
 25. A semiconductor device structure comprising a substrate having a silicon nitride layer formed thereon, said silicon nitride layer having a total thickness variation of about 2.6% or less.
 26. A silicon oxide layer deposited over a semiconductor substrate, the silicon oxide layer having a total thickness variation of about 4.8% or less.
 27. The silicon oxide layer of claim 26, comprising tetraethylorthosilicate (TEOS).
 28. The silicon oxide layer of claim 26, wherein said total thickness variation is about 4.5% or less.
 29. The silicon oxide layer of claim 26, wherein said total thickness variation is about 2.5% or less. 